Recently, lowering an electrical voltage applied to a gate oxide or a p-n junction in a MOS transistor has been required for retaining a reliability of the MOS transistor accompanying with progress of miniaturization in a fabricating process of a semiconductor device. However, lowering a source voltage of a system used by users can not be easily performed in considering compatibility with conventional products. Therefore, a method to generate a prescribed source voltage corresponding to a fabricating process by setting an internal voltage generation circuit in a semiconductor device is disclosed in Japanese Patent Publication (Kokai) No. 2002-298599, for example. Especially, the semiconductor devices included a DRAM (Dynamic Random Access Memory) cell or an EEPROM (Electrical Erasable PROM) cell has been required a plurality of the source voltage having complex voltage characteristics to retain characteristics of the circuit operation and reliability of the memory cell.
However, a conventional semiconductor device present a problem to be not able to measure a change of the internal voltage, when a load current is added to an output of the internal voltage generation circuit by an operation of the internal circuit. Such the load current has two kinds of currents. One is a current with raising the internal voltage by flowing from the source voltage and the other is a current with lowering the internal voltage by flowing out to the ground. An amount of the internal voltage by the current-flowing is dependent on architecture and drivability of the circuit. Therefore, when the drivability of the circuit is changed by the fabricating process or the like, the internal circuit presents a problem to be able to confirm on a margin of the circuit operation in the internal circuit being used by only an indirect method such as a simulation. Furthermore, the internal circuit presents another problem to be not able to confirm on a margin of the circuit operation produced by change of the fabricating process in the internal voltage generation circuit by a direct method.